A common requirement for an advanced electronic circuit and particularly for circuits manufactured as integrated circuits (“ICs”) in semiconductor processes is the need to accurately measure timing quantities such as jitter, duty cycle, pulse width, frequency, signal delays, and between signal timing. Use of on board timing measurement circuitry using prior art approaches often requires complex circuitry and significant silicon area. Further, in order to perform accurate measurements of delays, duty cycles, or pulse widths, calibration of the on board circuitry may be required, adding time and cost to the use of these approaches. The need to make such measurements for signals that are internal to an advanced integrated circuit of a system on a chip (“SoC”) device may make wafer probing or other external measurements difficult or impossible to perform.
One known time measurement approach, a time quantizer or time-to-digital converter circuit (“TDC”) uses delay taps or delay buffers with counters or shift registers. The delays may be of a common delay chained in series, or the delays may be in parallel but increase by the constant tau from one stage to the next. This TDC approach requires significant circuit area (silicon area), and often, also requires calibration after the integrated circuit (“IC”) or system on a chip (“SoC”) is manufactured. In one known approach a tapped vernier delay line with buffers coupled in series is used to clock a counter or a register chain, the data input is a signal with a pulse, and the tapped delay line also receives the same pulse. When the registers are clocked by the delayed pulse, the outputs of the stages that are, for example, a “1”, indicates the pulse width of the pulse. The digital output may be a thermometer code, for example.
These known approaches are also limited either in measurement range, or, in the fineness of the resolution. That is, in known approaches there is a design tradeoff between resolution, and range, of the measurement. For example, in a tapped delay line TDC the number of stages used forms a practical limit. When very fast buffers are used in the taps, or delays, of the delay line, the resolution is increased; but the measurement range is limited. On the other hand, the use of slower taps or delays may expand the maximum range that can be measured, but the smallest delay that can be measured (fine resolution) is then limited to a multiple of these delay times. Interpolation must be used to determine times of less than the minimum resolution, which is less accurate. Thus, design tradeoffs must be made to provide a practical measurement circuit with acceptable range, and resolution. Even so, these circuits require large silicon area. In another known approach, dual slope circuitry may be used and then converted to a digital quantity. The dual slope approaches of the prior art, which use analog delay circuitry with a digital conversion, also require significant circuitry to implement.
The known approaches may also require calibration. Calibration is needed because these delay measurements depend on the physical values of circuit elements, such as delay buffers, or other process dependent variables. Each integrated circuit manufactured in a semiconductor process will have some physical variation that affects the measurement; therefore each on board TDC circuit must be calibrated before measurements are made in order to achieve sufficient accuracy in the results. Calibration requires trimming or other adjustments, and additional bench time and often operator time to perform, and thus adds significant costs to the use of the measurement circuitry.
A continuing need thus exists for time measurement circuitry and methods that overcome the disadvantages of the prior art approaches.
The drawings, schematics and diagrams are illustrative and not intended to be limiting, but are examples of embodiments of the invention, are simplified for explanatory purposes, and are not drawn to scale.